Our main contributions are (i) a generic architecture for using GC/OTP modularly, and (ii) hardware implementation and efficiency analysis of GC/OTP evaluation. We implemented two FPGA-based prototypes: a system-on-a-programmable-chip with access to hardware crypto accelerator (suitable for smartcards and future smartphones), and a stand-alone hardware implementation (suitable for ASIC design). We chose AES as a representative complex function for implementation and measurements. As a result of this work, we are able to understand, evaluate and improve the practicality of employing GC/OTP as a leakage-resistance approach. Last, but not least, we believe that our work contributes to bringing together the results of both theoretical and practical communities.
Category / Keywords: Garbled Circuit, Hardware Implementation, Leakage-Resilience, One-Time Programs, Secure Function Evaluation Publication Info: Full version of CHES 2010 paper. Date: received 11 May 2010, last revised 17 Jun 2010 Contact author: thomas schneider at trust rub de Available format(s): PDF | BibTeX Citation Version: 20100617:125539 (All versions of this report) Short URL: ia.cr/2010/276 Discussion forum: Show discussion | Start new discussion