Paper 2010/173

Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA

Jean-Luc Beuchat, Eiji Okamoto, and Teppei Yamazaki

Abstract

We propose compact architectures of the SHA-$3$ candidates BLAKE-32 and BLAKE-64 for several FPGA families. We harness the intrinsic parallelism of the algorithm to interleave the computation of four instances of the $G_i$ function. This approach allows us to design an Arithmetic and Logic Unit with four pipeline stages and to achieve high clock frequencies. With careful scheduling, we completely avoid pipeline bubbles. For the time being, the designs presented in this work are the most compact ones for any of the SHA-3 candidates. We show for instance that a fully autonomous implementation of BLAKE-32 on a Xilinx Virtex-5 device requires 56 slices and two memory blocks.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Published elsewhere. Unknown where it was published
Keywords
SHA-3BLAKEfully autonomous implementationcompact implementationFPGA
Contact author(s)
jeanluc beuchat @ gmail com
History
2010-09-16: last of 2 revisions
2010-04-01: received
See all versions
Short URL
https://ia.cr/2010/173
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2010/173,
      author = {Jean-Luc Beuchat and Eiji Okamoto and Teppei Yamazaki},
      title = {Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA},
      howpublished = {Cryptology ePrint Archive, Paper 2010/173},
      year = {2010},
      note = {\url{https://eprint.iacr.org/2010/173}},
      url = {https://eprint.iacr.org/2010/173}
}
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