Cryptology ePrint Archive: Report 2010/124
A Hardware Wrapper for the SHA-3 Hash Algorithms
Brian Baldwin and Andrew Byrne and Liang Lu and Mark Hamilton and Neil Hanley and Maire O'Neill and William P. Marnane
Abstract: The second round of the NIST public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware is to be addressed during the second round of the contest.
For software implementations NIST specifies an application programming interface (API) along with reference implementation for each of the designs, thereby enabling quick and easy comparison and testing on software platforms, however no such specification was given for hardware analysis. In this paper we present a hardware wrapper interface which attempts to encompass all the competition entries (and indeed, hash algorithms in general) across any number of both FPGA and ASIC hardware platforms. This interface comprises communications and padding, and attempts to standardise the hashing algorithms to allow accurate and fair area, timing and power measurement between the different designs.
Category / Keywords: implementation / Hash, SHA-3, Hardware, Interface, FPGA, ASIC
Date: received 5 Mar 2010, last revised 5 Mar 2010
Contact author: brianb at rennes ucc ie
Available formats: PDF | BibTeX Citation
Note: All VHDL files associated with the hash wrapper will be made freely available by the authors at a later date to enable others to test their hash fuctions within a common wrapper.
Version: 20100306:041725 (All versions of this report)
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