Paper 2009/603
An FPGA Technologies Area Examination of the SHA-3 Hash Candidate Implementations
Brian Baldwin and William P. Marnane
Abstract
This paper presents an examination of the different FPGA architectures used to implement the various hash function candidates for the currently ongoing NIST-organised SHA-3 competition~\cite{Sha3NIST}. This paper is meant to be used as both a quick reference guide used in conjunction with the results table~\cite{Sha3zoo} as an aid in finding the ”best-fit” FPGA for a particular algorithm, as well as a helpful guide for explaining the many different terms and measurement units used in the various FPGA packages.
Metadata
- Available format(s)
- Category
- Implementation
- Publication info
- Published elsewhere. none
- Keywords
- hash functionsSHA-3FPGAXilinxAltera
- Contact author(s)
- brianb @ rennes ucc ie
- History
- 2009-12-09: received
- Short URL
- https://ia.cr/2009/603
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2009/603, author = {Brian Baldwin and William P. Marnane}, title = {An {FPGA} Technologies Area Examination of the {SHA}-3 Hash Candidate Implementations}, howpublished = {Cryptology {ePrint} Archive, Paper 2009/603}, year = {2009}, url = {https://eprint.iacr.org/2009/603} }