We show how to take advantage of the token to drastically reduce the communication complexity of SFE and computation load of the server.
Our main contribution is the detailed consideration of design decisions, optimizations, and trade-offs, associated with the setting and its strict hardware requirements for practical deployment. In particular, we model the token as a computationally weak device with small constant-size memory and limit communication between client and server.
We consider semi-honest, covert, and malicious adversaries. We show the feasibility of our protocols based on a FPGA implementation.
Category / Keywords: Garbled Circuits, Hardware Token, FPGA Implementation Publication Info: Full version of FC 2010 paper. Date: received 2 Dec 2009, last revised 8 Apr 2013 Contact author: thomas schneider at trust rub de Available formats: PDF | BibTeX Citation Version: 20130408:135941 (All versions of this report) Discussion forum: Show discussion | Start new discussion