Cryptology ePrint Archive: Report 2009/501
Fast Implementations of AES on Various Platforms
Joppe W. Bos, Dag Arne Osvik, and Deian Stefan
Abstract: This paper presents new software speed records for encryption and decryption using the block cipher AES-128 for different architectures. Target platforms are 8-bit AVR microcontrollers, NVIDIA
graphics processing units (GPUs) and the Cell broadband engine. The
new AVR implementation requires 124.6 and 181.3 cycles per byte for
encryption and decryption with a code size of less than two kilobyte.
Compared to the previous AVR records for encryption our code is 38
percent smaller and 1.24 times faster. The byte-sliced implementation
for the synergistic processing elements of the Cell architecture achieves speed of 11.7 and 14.4 cycles per byte for encryption and decryption. Similarly, our fastest GPU implementation, running on the GTX 295 and handling many input streams in parallel, delivers throughputs of 0.17 and 0.19 cycles per byte for encryption and decryption respectively. Furthermore, this is the first AES implementation for the GPU which implements both encryption and decryption.
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Date: received 16 Oct 2009, last revised 6 Nov 2009
Contact author: joppe bos at epfl ch
Available format(s): PDF | BibTeX Citation
Note: Fixed AVR cycle numbers in the abstract.
Version: 20091106:143155 (All versions of this report)
Short URL: ia.cr/2009/501
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