Cryptology ePrint Archive: Report 2009/342

FPGA Implementations of SHA-3 Candidates:CubeHash, Gr{\o}stl, L{\sc ane}, Shabal and Spectral Hash

Brian Baldwin and Andrew Byrne and Mark Hamilton and Neil Hanley and Robert P. McEvoy and Weibo Pan and William P. Marnane

Abstract: Abstract: Hash functions are widely used in, and form an important part of many cryptographic protocols. Currently, a public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware will form one of the evaluation criteria. In this paper, we focus on five of these candidate algorithms, namely CubeHash, Gr{\o}stl, L{\sc ane}, Shabal and Spectral Hash. Using Xilinx Spartan-3 and Virtex-5 FPGAs, we present architectures for each of these hash functions, and explore area-speed trade-offs in each design. The efficiency of various architectures for the five hash functions is compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first such comparison of these SHA-3 candidates in the literature.

Category / Keywords: implementation, hash functions, SHA-3

Publication Info: The 12th Euromicro Conference on Digital System Design- DSD 2009, IEEE Computer Society

Date: received 11 Jul 2009, last revised 31 Jul 2009

Contact author: brianb at rennes ucc ie

Available format(s): PDF | BibTeX Citation

Note: This is an updated paper of the version that will appear at DSD2009. Also a misplacement was found in the second Throughput-Area graph (Fig 12) design #19 is on the graph as 0.45 (Gbps), when it should be 1.45 (as described in Table 4). The Figure has been updated with the correct value for this version.

Version: 20090731:140934 (All versions of this report)

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