Cryptology ePrint Archive: Report 2009/159

Hardware Implementation of the SHA-3 Candidate Skein

Stefan Tillich

Abstract: Skein is a submission to the NIST SHA-3 hash function competition which has been optimized towards implementation in modern 64-bit processor architectures. This paper investigates the performance characteristics of a high-speed hardware implementation of Skein with a 0.18\,\textmu}m standard-cell library and on different modern FPGAs. The results allow a first comparison of the hardware performance figures of full Skein with other SHA-3 candidates.

Category / Keywords: implementation / SHA-3, Skein, high-speed, hardware, standard-cell library, FPGA

Publication Info: First publication via eprint.

Date: received 6 Apr 2009

Contact author: Stefan Tillich at iaik tugraz at

Available format(s): PDF | BibTeX Citation

Version: 20090407:112953 (All versions of this report)

Short URL: ia.cr/2009/159

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