Paper 2009/122
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, and Francisco Rodríguez-Henríquez
Abstract
This paper is devoted to the design of fast parallel accelerators
for the cryptographic Tate pairing in characteristic three over
supersingular elliptic curves. We propose here a novel hardware
implementation of Miller's loop based on a pipelined Karatsuba-Ofman
multiplier. Thanks to a careful selection of algorithms for computing the tower field arithmetic associated to the Tate pairing, we manage to keep the pipeline busy. We also describe the strategies we
considered to design our parallel multiplier. They are included in a
VHDL code generator allowing for the exploration of a wide range of
operators. Then, we outline the architecture of a coprocessor for
the Tate pairing over
Metadata
- Available format(s)
-
PDF
- Category
- Implementation
- Publication info
- Published elsewhere. Unknown where it was published
- Keywords
- Tate pairing
pairingelliptic curvefinite field arithmeticKaratsuba-Ofman multiplierhardware acceleratorFPGA - Contact author(s)
- jeanluc beuchat @ gmail com
- History
- 2009-08-04: last of 2 revisions
- 2009-03-15: received
- See all versions
- Short URL
- https://ia.cr/2009/122
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2009/122, author = {Jean-Luc Beuchat and Jérémie Detrey and Nicolas Estibals and Eiji Okamoto and Francisco Rodríguez-Henríquez}, title = {Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers}, howpublished = {Cryptology {ePrint} Archive, Paper 2009/122}, year = {2009}, url = {https://eprint.iacr.org/2009/122} }