Cryptology ePrint Archive: Report 2007/016
Sean O'Neil and Benjamin Gittins and Howard A. Landman
Abstract: VEST (Very Efficient Substitution-Transposition) is a set of families of counter-assisted substitution-transposition ciphers designed and optimised specifically for ASIC and FPGA hardware. VEST ciphers provide fast scalable keystream generation, authenticated encryption and collision-resistant hashing at a very low cost in area and power consumption. All VEST ciphers support variable-length keys and IVs and are naturally very slow in software. Cores of VEST ciphers can be viewed as light-weight T-functions or large bijective nonlinear feedback shift registers (NLFSRs) with massively parallel feedback, assisted by a nonlinear residue number system (RNS) based counter with a very long period. Four VEST cipher family trees are introduced: 80 bit secure VEST4-80, 128 bit secure VEST8-128, 160 bit secure VEST16-160 and 256 bit secure VEST32-256, returning 4 to 32 bits of output per clock cycle while occupying ~3K to ~28K ASIC gates.
Category / Keywords: secret-key cryptography / stream cipher, hash function
Publication Info: Corrected eSTREAM Phase II submission
Date: received 21 Jan 2007, last revised 26 Jan 2007, withdrawn 3 Apr 2007
Contact author: sean at cryptolib com
Available format(s): (-- withdrawn --)
Note: The paper has been withdrawn by the editors at the request of Allen Evans (firstname.lastname@example.org), patent attorney, acting for Benjamin Gittins, Synaptic Laboratories Limited and Abigail Properties Limited. The author Sean O'Neil has agreed to the withdrawal.
Version: 20070403:225409 (All versions of this report)
Short URL: ia.cr/2007/016
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