Paper 2006/371

Hardware Implementation of the ηT Pairing in Characteristic 3

Robert Ronan, Colm o hEigeartaigh, Colin Murphy, Tim Kerins, and Paulo S. L. M. Barreto

Abstract

Recently, there have been many proposals for secure and novel cryptographic protocols that are built on bilinear pairings. The ηT pairing is one such pairing and is closely related to the Tate pairing. In this paper we consider the efficient hardware implementation of this pairing in characteristic 3. All characteristic 3 operations required to compute the pairing are outlined in detail. An efficient, flexible and reconfigurable processor for the ηT pairing in characteristic 3 is presented and discussed. The processor can easily be tailored for a low area implementation, for a high throughput implementation, or for a balance between the two. Results are provided for various configurations of the processor when implemented over the field F397 on an FPGA. As far as we are aware, the processor returns the first characteristic 3 pairing in hardware that includes a final exponentiation to a unique value.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Published elsewhere. Unknown where it was published
Keywords
pairingcharacteristic 3elliptic curvereconfigurable processorFPGA
Contact author(s)
robertcronan @ gmail com
History
2006-11-03: received
Short URL
https://ia.cr/2006/371
License
Creative Commons Attribution
CC BY

BibTeX 

@misc{cryptoeprint:2006/371,
      author = {Robert Ronan and Colm o hEigeartaigh and Colin Murphy and Tim Kerins and Paulo S.  L.  M.  Barreto},
      title = {Hardware Implementation of the $\e{ta_T}$ Pairing in Characteristic 3},
      howpublished = {Cryptology {ePrint} Archive, Paper 2006/371},
      year = {2006},
      url = {https://eprint.iacr.org/2006/371}
}
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