Cryptology ePrint Archive: Report 2006/042
Application of LFSRs for Parallel Sequence Generation in Cryptologic Algorithms
Sourav Mukhopadhyay and Palash Sarkar
Abstract: We consider the problem of efficiently generating sequences in hardware for use in certain cryptographic algorithms. The conventional method of doing this is to use a counter. We show that sequences generated by linear feedback shift registers (LFSRs) can be tailored to suit the appropriate algorithms. For hardware implementation, this reduces both time and chip area. As a result, we are able to suggest improvements to
the design of DES Cracker built by the Electronic Frontier Foundation in 1998; provide an efficient strategy for generating start points in time-memory trade/off attacks; and present an improved parallel hardware implementation of a variant of the counter mode of operation of a block cipher.
Category / Keywords: secret-key cryptography / DES Cracker, TMTO, Counter Mode of Operation, LFSR
Date: received 6 Feb 2006, last revised 28 Feb 2006
Contact author: palash at isical ac in
Available format(s): PDF | BibTeX Citation
Note: Earlier work on use of LFSRs for exhaustive key search was kindly pointed out to us by David Wagner. The "Related Works" portion of the current paper discusses this point.
Version: 20060228:070341 (All versions of this report)
Short URL: ia.cr/2006/042
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