Cryptology ePrint Archive: Report 2005/415

A Presentation on VEST Hardware Performance, Chip Area Measurements, Power Consumption Estimates and Benchmarking in Relation to the AES, SHA-256 and SHA-512

Benjamin Gittins and Howard A. Landman and Sean O'Neil and Ron Kelson

Abstract: A wide-sweeping multi-dimensional analysis and comparison between VEST and the hardware implementations of the AES, AES-HMAC and SHA-2 primitives.

Category / Keywords: implementation / stream ciphers, hash functions, authenticated encryption, message digest, MAC, message authentication code, fastest hardware cipher, NLFSR, parallel feedback, RNS, residue number system, AES, SHA-256, SHA-512, SHA-2, FPGA, ASIC

Publication Info: posted on ECRYPT, not published previously

Date: received 17 Nov 2005, last revised 3 Apr 2007, withdrawn 3 Apr 2007

Contact author: sean at cryptolib com

Available format(s): (-- withdrawn --)

Version: 20070403:151733 (All versions of this report)

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