Cryptology ePrint Archive: Report 2005/280

Partitioned Cache Architecture as a Side-Channel Defence Mechanism

D. Page

Abstract: Recent research has produced a number of viable side-channel attack methods based on the data-dependant behaviour of microprocessor cache memory. Most proposed defence mechanisms are software based and mainly act to increase the attackers workload rather than obviate the attack entirely. In this paper we investigate the use of a configurable cache architecture to provide hardware assisted defence. By exposing the cache to the processor and allowing it to be dynamically configured to match the needs of a given application, we provide opportunity for higher performance as well as security.

Category / Keywords: implementation / side-channel attack, cache architecture

Date: received 22 Aug 2005

Contact author: page at cs bris ac uk

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Version: 20050825:073958 (All versions of this report)

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