Cryptology ePrint Archive: Report 2005/146

A High Speed Architecture for Galois/Counter Mode of Operation (GCM)

Bo Yang, Sambit Mishra, Ramesh Karri

Abstract: In this paper we present a fully pipelined high speed hardware architecture for Galois/Counter Mode of Operation (GCM) by analyzing the data dependencies in the GCM algorithm at the architecture level. We show that GCM encryption circuit and GCM authentication circuit have similar critical path delays resulting in an efficient pipeline structure. The proposed GCM architecture yields a throughput of 34 Gbps running at 271 MHz using a 0.18 um CMOS standard cell library.

Category / Keywords: Authenticated Encryption Mode, GCM

Date: received 17 May 2005, last revised 3 Jun 2005

Contact author: smishr01 at utopia poly edu

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Version: 20050603:155859 (All versions of this report)

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