Paper 2004/346

Random Switching Logic: A Countermeasure against DPA based on Transition Probability

Daisuke Suzuki, Minoru Saeki, and Tetsuya Ichikawa

Abstract

In this paper, we propose a new model for directly evaluating DPA leakage from logic information in CMOS circuits.This model is based on the transition probability for each gate, and is naturally applicable to various actual devices for simulating power analysis. We also report on our study of the effects of the previously known countermeasures on both our model and FPGA, and show the possibility of leaking information, which is caused by strict precondition for implementing a secure circuit. Furthermore, we present an efficient countermeasure, \textit{Random Switching Logic}(RSL), for relaxing the precondition, and show that RSL makes a cryptographic circuit secure through evaluation on both our model and FPGA.

Metadata
Available format(s)
PDF PS
Category
Implementation
Publication info
Published elsewhere. Unknown where it was published
Keywords
side-channel attaksCMOSleakage modeltransition probability
Contact author(s)
dice @ iss isl melco co jp
History
2004-12-13: received
Short URL
https://ia.cr/2004/346
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2004/346,
      author = {Daisuke Suzuki and Minoru Saeki and Tetsuya Ichikawa},
      title = {Random Switching Logic: A Countermeasure against DPA based on Transition Probability},
      howpublished = {Cryptology ePrint Archive, Paper 2004/346},
      year = {2004},
      note = {\url{https://eprint.iacr.org/2004/346}},
      url = {https://eprint.iacr.org/2004/346}
}
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