Cryptology ePrint Archive: Report 2004/068

Synthesis of Secure FPGA Implementations

Kris Tiri and Ingrid Verbauwhede

Abstract: This paper describes the synthesis of Dynamic Differential Logic to increase the resistance of FPGA implementations against Differential Power Analysis. The synthesis procedure is developed and a detailed description is given of how EDA tools should be used appropriately to implement a secure digital design flow. Compared with an existing technique to implement Dynamic Differential Logic on FPGA, the technique saves a factor 2 in slice utilization. Experimental results also indicate that a secure version of the AES encryption algorithm can now be implemented with a mere 50% increase in time delay and 90% increase in slice utilization when compared with a normal non-secure single ended implementation.

Category / Keywords: implementation / differential power analysis, FPGA, synthese

Date: received 28 Feb 2004

Contact author: tiri at ee ucla edu

Available format(s): PDF | BibTeX Citation

Version: 20040229:092010 (All versions of this report)

Short URL: ia.cr/2004/068

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