Cryptology ePrint Archive: Report 2004/066
A Dynamic and Differential CMOS Logic Style to Resist Power and Timing Attacks on Security ICís.
Kris Tiri and Ingrid Verbauwhede
Abstract: We present a dynamic and differential CMOS logic style, which has a signal independent switching behavior. It is shown that during each clock cycle, power consumption and all circuit characteristics, such as leakage current, instantaneous current and input-output delay are identical and independent of the logic value and the sequence of the input data. Implementing the encryption module in this logic will protect it against any Side Channel Attack that takes advantage of power, timing and leakage information. We have built a set of logic gates and a flip-flop needed for cryptographic functions and implemented a larger module, for which area, total power consumption and variation on the power consumption have been compared with implementations in Static Complementary CMOS logic, genuine Dynamic and Differential Logic and Current Mode Logic.
Category / Keywords: implementation / differential power analysis, smart cards, circuit styles
Date: received 28 Feb 2004
Contact author: tiri at ee ucla edu
Available format(s): PDF | BibTeX Citation
Version: 20040229:091704 (All versions of this report)
Discussion forum: Show discussion | Start new discussion
[ Cryptology ePrint archive ]