Paper 2000/051

Reducing the Gate Count of Bitslice DES

Matthew Kwan

Abstract

This paper describes various techniques to reduce the number of logic gates needed to implement the DES S-boxes in bitslice software. Using standard logic gates, an average of 56 gates per S-box was achieved, while an average of 51 was produced when non-standard gates were utilized. This is an improvement over the previous best result, which used an average of 61 non-standard gates.

Metadata
Available format(s)
PS
Category
Implementation
Publication info
Published elsewhere. Unknown where it was published
Keywords
DES
Contact author(s)
mkwan @ darkside com au
History
2000-10-09: received
Short URL
https://ia.cr/2000/051
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2000/051,
      author = {Matthew Kwan},
      title = {Reducing the Gate Count of Bitslice DES},
      howpublished = {Cryptology ePrint Archive, Paper 2000/051},
      year = {2000},
      note = {\url{https://eprint.iacr.org/2000/051}},
      url = {https://eprint.iacr.org/2000/051}
}
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